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final publication# 18805 rev: d amendment/ 0 issue date: april 1997 AM29F016 16-megabit (2,097,152 x 8-bit) cmos 5.0 volt-only, sector erase flash memory distinctive characteristics n 5.0 volt 10% for read and write operations minimizes system level power requirements n compatible with jedec-standards pinout and software compatible with single-power supply flash superior inadvertent write protection n 48-pin tsop n 44-pin so n minimum 100,000 write/erase cycles guaranteed n high performance 70 ns maximum access time n sector erase architecture uniform sectors of 64 kbytes each any combination of sectors can be erased. also supports full chip erase n group sector protection hardware method that disables any combination of sector groups from write or erase operations (a sector group consists of 4 adjacent sectors of 64 kbytes each) n embedded erase algorithms automatically pre-programs and erases the chip or any sector n embedded program algorithms automatically programs and verifies data at specified address n data polling and toggle bit feature for detection of program or erase cycle completion n ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion n erase suspend/resume supports reading or programming data to a sector not being erased n low power consumption 25 ma typical active read current 30 ma typical program/erase current n enhanced power management for standby mode <1 m a typical standby current standard access time from standby mode n hardware reset pin resets internal state machine to the read mode general description the AM29F016 is a 16 mbit, 5.0 volt-only flash memory organized as 2 megabytes of 8 bits each. the 2 mbytes of data is divided into 32 sectors of 64 kbytes for flexible erase capability. the 8 bits of data appear on dq0Cdq7. the AM29F016 is offered in 48-pin tsop and 44-pin so packages. this device is designed to be programmed in-system with the standard system 5.0 volt v cc supply. 12.0 volt v pp is not required for program or erase operations. the device can also be reprogrammed in standard eprom programmers. the standard AM29F016 offers access times of 70 ns, 90 ns, 120 ns, and 150 ns, allowing high-speed microprocessors to operate without wait states. to eliminate bus contention, the device has separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. the AM29F016 is entirely command set compatible with the jedec single-power supply flash standard. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine that controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 12.0 volt flash or eprom devices. the AM29F016 is programmed by executing the pro- gram command sequence. this will invoke the embed-
2 AM29F016 ded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. erase is accomplished by executing the erase command sequence. this will in- voke the embedded erase algorithm which is an inter- nal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. this device also features a sector erase architecture. this allows for sectors of memory to be erased and re- programmed without affecting the data contents of other sectors. a sector is typically erased and verified within one second. the AM29F016 is erased when shipped from the factory. the AM29F016 device also features hardware sector group protection. this feature will disable both pro- gram and erase operations in any combination of eight sector groups of memory. a sector group consists of four adjacent sectors grouped in the following pattern: sectors 0C3, 4C7, 8C11, 12C15, 16C19, 20C23, 24C27, and 28C31. amd has implemented an erase suspend feature that enables the user to put erase on hold for any period of time to read data from, or program data to, a sector that was not being erased. thus, true background erase can be achieved. the device features single 5.0 volt power supply oper- ation for both read and write functions. internally gen- erated and regulated voltages are provided for the program and erase operations. a low v cc detector au- tomatically inhibits write operations during power tran- sitions. the end of program or erase is detected by the ry/by pin, data polling of dq7, or by the toggle bit i (dq6).once the end of a program or erase cycle has been completed, the device automatically resets to the readmode. the AM29F016 also has a hardware reset pin. when this pin is driven low, execution of any embed- ded program algorithm or embedded erase algorithm will be terminated. the internal state machine will then be reset into the read mode. the reset pin may be tied to the system reset circuitry. therefore, if a system reset occurs during the embedded program algorithm or embedded erase algorithm, the device will be auto- matically reset to the read mode. this will enable the systems microprocessor to read the boot-up firmware from the flash memory. amds flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. the AM29F016 memory electrically erases all bits within a sector simultaneously via fowler-nordheim tunneling. the bytes are pro- grammed one byte at a time using the eprom pro- gramming mechanism of hot electron injection. flexible sector-erase architecture n thirty two 64 kbyte sectors n eight sector groups each of which consists of 4 adjacent sectors in the following pattern: sectors 0 C 3, 4 C 7, 8 C 11, 12 C 15, 16 C 19, 20 C 23, 24 C 27, and 28 C 31. n individual-sector or multiple-sector erase capability n sector group protection is user-definable 18805d-1 sa31 sa30 sa29 sa28 sa3 sa2 sa1 sa0 1fffffh 1effffh 1dffffh 1cffffh 1bffffh 1affffh 19ffffh 18ffffh 17ffffh 16ffffh 15ffffh 14ffffh 13ffffh 12ffffh 11ffffh 10ffffh 1fffffh 1effffh 1dffffh 1cffffh 1bffffh 1affffh 09ffffh 08ffffh 07ffffh 06ffffh 05ffffh 04ffffh 03ffffh 02ffffh 01ffffh 00ffffh 000000h sector group 7 sector group 0 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 32 sectors total
AM29F016 3 product selector guide block diagram family part no. ordering part no: v cc = 5.0 volt 5% -75 v cc = 5.0 volt 10% -90 -120 -150 max access time (ns) 70 90 120 150 ce (e ) access (ns) 70 90 120 150 oe (g ) access (ns) 40 40 50 75 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we ce oe stb stb dq0 C dq7 sector switches ry/by reset data latch y-gating cell matrix 18805d-2 address latch a0Ca20
4 AM29F016 connection diagrams 3 4 5 2 1 9 10 11 12 13 39 38 37 36 35 20 19 18 21 22 7 8 34 33 23 24 6 44 43 32 14 25 42 41 40 15 16 17 26 27 28 31 30 29 a8 a7 a6 a5 a4 nc nc v ss v ss nc a3 dq3 a11 a10 a9 dq2 dq1 dq0 a2 a1 a0 a15 a16 a17 a18 a19 nc nc v cc dq4 ce a20 dq5 a12 a13 a14 dq6 dq7 ry/by nc we oe reset v cc so 18805d-3a
AM29F016 5 connection diagrams 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 nc dq2 nc a20 nc we oe ry/ by dq7 dq1 dq0 a0 a1 a2 a3 nc nc dq6 dq5 dq4 v cc v ss v ss dq3 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 nc a10 nc a19 a18 a17 a16 a15 a14 a13 a12 ce v cc nc reset a11 nc a9 a8 a7 a6 a5 a4 nc 18805d-3 standard tsop 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 nc dq2 nc a20 nc we oe ry/ by dq7 dq1 dq0 a0 a1 a2 a3 nc nc dq6 dq5 dq4 v cc v ss v ss dq3 nc a10 nc a19 a18 a17 a16 a15 a14 a13 a12 ce v cc nc reset a11 nc a9 a8 a7 a6 a5 a4 nc 18805d-4 reverse tsop
6 AM29F016 pin configuration a0Ca20 = 21 addresses ce = chip enable dq0Cdq7 = 8 data inputs/outputs nc = pin not connected internally oe = output enable reset = hardware reset pin, active low ry/by = ready/busy output v cc = +5.0 volt single-power supply ( 10% for -90, -120, -150) or ( 5% for -95) v ss = device ground we = write enable logic symbol 21 8 dq0Cdq7 a0Ca20 ce (e ) oe (g ) we (w ) 18805d-5 reset ry/by
AM29F016 7 ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of: temperature range c= commercial (0 c to +70 c) i = industrial (-40 c to +85 c) package type e = 48-pin thin small outline package (tsop) standard pinout (ts 048) f = 48-pin thin small outline package (tsop) reverse pinout (tsr048) s = 44-pin small outline package (so 044) device number/description AM29F016 16 megabit (2m x 8-bit) cmos flash memory 5.0 volt-only program and erase AM29F016 -75 e i valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. optional processing blank = standard processing b = burn-in b speed option see product selector guide and valid combinations valid combinations AM29F016-75 ec, ei, fc, fi, sc, si AM29F016-90 AM29F016-120 ec, ecb, ei, eib, fc, fcb, fi, fib, sc, scb, si, sib AM29F016-150
8 AM29F016 table 1. AM29F016 user bus operations legend: l = logic 0, h = logic 1, x = dont care. see dc characteristics for voltage levels. notes: 1. manufacturer and device codes may also be accessed via a command register write sequence. refer to table 5. 2. refer to the section on sector group protection. read mode the AM29F016 has two control functions which must be satisfied in order to obtain data at the outputs. ce is the power control and should be used for device selec- tion. oe is the output control and should be used to gate data to the output pins if the device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins (assuming the addresses have been stable for at least t acc Ct oe time). standby mode there are two ways to implement the standby mode on the AM29F016 device, one using both the ce and reset pins; the other via the reset pin only. when using both pins, a cmos standby mode is achieved with ce and reset inputs both held at v cc 0.3 v. under this condition the current is typically reduced to less than 1 m a. a ttl standby mode is achieved with ce and reset pins held at v ih . under this condition the current is typically reduced to 200 m a. the device can be read with standard access time (t ce ) from either of these standby modes . when using the reset pin only, a cmos standby mode is achieved with reset input held at v ss 0.3 v (ce = dont care). under this condition the current is typ- ically reduced to less than 1 m a. a ttl standby mode is achieved with reset pin held at v il (ce = dont care). under this condition the current is typically reduced to less than 200 m a. once the reset pin is taken high, the device requires 50 ns of wake up time before out- puts are valid for read access. in the standby mode the outputs are in the high imped- ance state, independent of the oe input. output disable with the oe input at a logic high level (v ih ), output from the device is disabled. this will cause the output pins to be in a high impedance state. operation ce oe we a0 a1 a6 a9 dq0 C dq7 reset autoselect, amd manuf. code (1) l l h l l l v id code h autoselect device code (1) l l h h l l v id code h read l l x a0 a1 a6 a9 d out h standby h x x x x x x high z h output disable lhhxxx x high z h write l h l a0 a1 a6 a9 d in h enable sector group protect (2) l v id lxxxv id xh verify sector group protect (2) l l h l h l v id code h temporary sector group unprotect x x x x x x x x v id hardware reset/standby xxxxxx x high z l
AM29F016 9 autoselect the autoselect mode allows the reading of a binary code from the device and will identify its manufacturer and type. this mode is intended for use by program- ming equipment for the purpose of automatically matching the device to be programmed with its corre- sponding programming algorithm. this mode is func- tional over the entire temperature range of the device. to activate this mode, the programming equipment must force v id (11.5 v to 12.5 v) on address pin a9. two identifier bytes may then be sequenced from the device outputs by toggling address a0 from v il to v ih . all addresses are dont cares except a0, a1, and a6 (seetable 2). the manufacturer and device codes may also be read via the command register, for instances when the AM29F016 is erased or programmed in a system with- out access to high voltage on the a9 pin. the command sequence is illustrated in table 5 (see autoselect com- mand sequence). byte 0 (a0 = v il ) represents the manufacturers code (amd = 01h) and byte 1 (a0 = v ih ) the device identifier code for AM29F016 = adh. these two bytes are given in the table below. all identifiers for manufacturer and device will exhibit odd parity with dq7 defined as the parity bit. in order to read the proper device codes when executing the autoselect, a1 must be v il (see ta b l e 2 ) . the autoselect mode also facilitates the determination of sector group protection in the system. by performing a read operation at the address location xx02h with the higher order address bits a18, a19, and a20 set to the desired sector group address, the device will return 01h for a protected sector group and 00h for a non-protected sector group. table 2. AM29F016 sector protection verify autoselect codes * outputs 01h at protected sector addresses type a18 to a20 a6 a1 a0 code (hex) dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 manufacturer code C amdxxxv il v il v il 01h00000001 AM29F016 device x x x v il v il v ih adh10101101 sector group protection sector group address v il v ih v il 01h*00000001
10 AM29F016 table 3. sector address table a20 a19 a18 a17 a16 address range sa0 0 0 0 0 0 000000h-00ffffh sa1 0 0 0 0 1 010000h-01ffffh sa2 0 0 0 1 0 020000h-02ffffh sa3 0 0 0 1 1 030000h-03ffffh sa4 0 0 1 0 0 040000h-04ffffh sa5 0 0 1 0 1 050000h-05ffffh sa6 0 0 1 1 0 060000h-06ffffh sa7 0 0 1 1 1 070000h-07ffffh sa8 0 1 0 0 0 080000h-08ffffh sa9 0 1 0 0 1 090000h-09ffffh sa10 0 1 0 1 0 0a0000h-0affffh sa11 0 1 0 1 1 0b0000h-0bffffh sa12 0 1 1 0 0 0c0000h-0cffffh sa13 0 1 1 0 1 0d0000h-0dffffh sa14 0 1 1 1 0 0e0000h-0effffh sa15 0 1 1 1 1 0f0000h-0fffffh sa16 1 0 0 0 0 100000h-10ffffh sa17 1 0 0 0 1 110000h-11ffffh sa18 1 0 0 1 0 120000h-12ffffh sa19 1 0 0 1 1 130000h-13ffffh sa20 1 0 1 0 0 140000h-14ffffh sa21 1 0 1 0 1 150000h-15ffffh sa22 1 0 1 1 0 160000h-16ffffh sa23 1 0 1 1 1 170000h-17ffffh sa24 1 1 0 0 0 180000h-18ffffh sa25 1 1 0 0 1 190000h-19ffffh sa26 1 1 0 1 0 1a0000h-1affffh sa27 1 1 0 1 1 1b0000h-1bffffh sa28 1 1 1 0 0 1c0000h-1cffffh sa29 1 1 1 0 1 1d0000h-1dffffh sa30 1 1 1 1 0 1e0000h-1effffh sa31 1 1 1 1 1 1f0000h-1fffffh
AM29F016 11 table 4. sector group addresses write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any ad- dressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the command register is written to by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later; while data is latched on the rising edge of we or ce , whichever happens first. standard micro- processor write timings are used. refer to ac write characteristics and the erase/pro- gramming waveforms for specific timing parameters. sector group protection the AM29F016 features hardware sector group protec- tion. this feature will disable both program and erase operations in any combination of eight sector groups of memory. each sector group consists of four adjacent sectors grouped in the following pattern: sectors 0 C 3, 4 C 7, 8 C 11, 12 C 15, 16 C 19, 20 C 23, 24 C 27, and 28 C 31 (see table 4). the sector group protect feature is en- abled using programming equipment at the users site. the device is shipped with all sector groups unpro- tected. alternatively, amd may program and protect sector groups in the factory prior to shipping the device (amds expressflash? service). it is possible to determine if a sector group is protected in the system by writing an autoselect command. per- forming a read operation at the address location xx02h, where the higher order address bits a18, a19, and a20 is the desired sector group address, will pro- duce a logical 1 at dq0 for a protected sector group. see table 2 for autoselect codes. temporary sector group unprotect this feature allows temporary unprotection of previ- ously protected sector groups of the AM29F016 device in order to change data in-system. the sector group unprotect mode is activated by setting the reset pin to high voltage (12v). during this mode, formerly pro- tected sector groups can be programmed or erased by selecting the sector group addresses. once the 12 v is taken away from the reset pin, all the previously pro- tected sector groups will be protected again. refer to figures 15 and 16. command definitions device operations are selected by writing specific ad- dress and data sequences into the command register. writing incorrect address and data values or writ- ing them in the improper sequence will reset the device to the read mode . table 5 defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. moreover, both reset/read commands are functionally equivalent, resetting the device to the read mode. a20 a19 a18 sectors sga0 0 0 0 sa0 C sa3 sga1 0 0 1 sa4 C sa7 sga2 0 1 0 sa8 C sa11 sga3 0 1 1 sa12 C sa15 sga4 1 0 0 sa16 C sa19 sga5 1 0 1 sa20 C sa23 sga6 1 1 0 sa24 C sa27 sga7 1 1 1 sa28 C sa31
12 AM29F016 table 5. AM29F016 command definitions notes: 1. bus operations are defined in table 1. 2. ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we pulse. sa= address of the sector to be erased. the combination of a20, a19, a18, a17, and a16 will uniquely select any sector. 3. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of we . 4. read and byte program functions to non-erasing sectors are allowed in the erase suspend mode. 5. address bits a15, a14, a13, a12 and a11 = x, x = dont care. read/reset command the read or reset operation is initiated by writing the read/reset command sequence into the command reg- ister. microprocessor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. the device will automatically power-up in the read/ reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value en- sures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and waveforms for the specific timing parameters. autoselect command flash memories are intended for use in applications where the local cpu can alter memory contents. as such, manufacture and device codes must be accessible while the device resides in the target sys- tem. prom programmers typically access the signa- ture codes by raising a9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally a desirable system design practice. the device contains an autoselect command operation to supplement traditional prom programming methodology. the operation is initiated by writing the autoselect command sequence into the command reg- ister. following the command write, a read cycle from address xx00h retrieves the manufacturer code of 01h. a read cycle from address xx01h returns the de- vice code adh (see table 2). all manufacturer and device codes will exhibit odd par- ity with dq7 defined as the parity bit. furthermore, the write protect status of sectors can be read in this mode. scanning the sector group addresses (a18, a19, and a20) while (a6, a1, a0) = (0, 1, 0) will produce a logical 1 at device output dq0 for a protected sector group. to terminate the operation, it is necessary to write the read/reset command sequence into the register. byte programming the device is programmed on a byte-by-byte basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data write cycles. ad- dresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) be- gins programming using the embedded program algo- command sequence read/reset bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr data addr data addr data addr data addr data addr data reset/read 1 xxxxh f0h reset/read 3 5555h aah 2aaah 55h 5555h f0h ra rd autoselect 3 5555h aah 2aaah 55h 5555h 90h byte program 4 5555h aah 2aaah 55h 5555h a0h pa data chip erase 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h sector erase 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa 30h erase suspend 1 xxxxh b0h erase resume 1 xxxxh 30h
AM29F016 13 rithm. upon executing the algorithm, the system is not required to provide further controls or timings. the de- vice will automatically provide adequate internally gen- erated program pulses and verify the programmed cell margin. this automatic programming operation is completed when the data on dq7 (also used as data polling) is equivalent to the data written to this bit at which time the device returns to the read mode and addresses are no longer latched (see table 6, write operation sta- tus). therefore, the device requires that a valid address to the device be supplied by the system at this particu- lar instance of time for data polling operations. data polling must be performed at the memory location which is being programmed. any commands written to the chip during the embed- ded program algorithm will be ignored. if a hardware reset occurs during the programming operation, the data at that particular location will be corrupted. programming is allowed in any sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may ei- ther hang up the device or result in an apparent suc- cess according to the data polling algorithm but a read from reset/read mode will show that the data is still 0. only erase operations can convert 0s to 1s. figure 1 illustrates the embedded programming algo- rithm using typical command strings and bus operations. chip erase chip erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. the automatic erase begins on the rising edge of the last we pulse in the command sequence and termi- nates when the data on dq7 is 1 (see write opera- tion status section) at which time the device returns to read mode. figure 2 illustrates the embedded erase algorithm using typical command strings and bus operations. sector erase sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sec- tor) is latched on the falling edge of we , while the com- mand (30h) is latched on the rising edge of we . after a time-out of 50 m s from the rising edge of the last sec- tor erase command, the sector erase operation will begin. multiple sectors may be erased sequentially by writing the six bus cycle operations as described above. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than 50 m s otherwise that command will not be ac- cepted and erasure will start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-en- abled after the last sector erase command is written. a time-out of 50 m s from the rising edge of the last we will initiate the execution of the sector erase command(s). if another falling edge of the we occurs within the 50 m s time-out window the timer is reset. (monitor dq3 to determine if the sector erase timer window is still open, see section dq3, sector erase timer.) any command other than sector erase or erase suspend during this period will reset the device to the read mode, ignoring the previous command string. in that case, restart the erase on those sectors and allow them to com- plete.(refer to the write operation status section for dq3, sector erase timer, operation.) loading the sec- tor erase buffer may be done in any sequence and with any number of sectors (0 to 31). sector erase does not require the user to program the device prior to erase. the device automatically pro- grams all memory locations in the sector(s) to be erased prior to electrical erase. when erasing a sector or sectors the remaining unselected sectors are not af- fected. the system is not required to provide any con- trols or timings during these operations. the automatic sector erase begins after the 50 m s time out from the rising edge of the we pulse for the last sector erase command pulse and terminates when the data on dq7, data polling, is 1 (see write operation status section) at which time the device returns to the read mode. data polling must be performed at an ad- dress within any of the sectors being erased. figure 2 illustrates the embedded erase algorithm using typical command strings and bus operations. erase suspend the erase suspend command allows the user to inter- rupt a sector erase operation and then perform data reads or programs to a sector not being erased. this command is applicable only during the sector erase operation which includes the time-out period for sector erase. the erase suspend command will be ignored if written during the chip erase operation or embedded
14 AM29F016 program algorithm. writing the erase suspend com- mand during the sector erase time-out results in imme- diate termination of the time-out period and suspension of the erase operation. any other command written during the erase suspend mode will be ignored except the erase resume com- mand. writing the erase resume command resumes the erase operation. the addresses are dont-cares when writing the erase suspend or erase resume command. when the erase suspend command is written during the sector erase operation, the device will take a max- imum of 15 m s to suspend the erase operation. when the device has entered the erase-suspended mode, the ry/by output pin and the dq7 bit will be at logic 1, and dq6 will stop toggling. the user must use the ad- dress of the erasing sector for reading dq6 and dq7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ig- nored. when the erase operation has been suspended, the device defaults to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-sus- pended. successively reading from the erase-sus- pended sector while the device is in the erase-suspend-read mode will cause dq2 to toggle. (see the section on dq2). after entering the erase-suspend-read mode, the user can program the device by writing the appropriate com- mand sequence for byte program. this program mode is known as the erase-suspend-program mode. again, programming in this mode is the same as programming in the regular byte program mode except that the data must be programmed to sectors that are not erase-sus- pended. successively reading from the erase-sus- pended sector while the device is in the erase-suspend-program mode will cause dq2 to tog- gle. the end of the erase-suspended program opera- tion is detected by the ry/by output pin, data polling of dq7, or by the toggle bit i (dq6) which is the same as the regular byte program operation. note that dq7 must be read from the byte program address while dq6 can be read from any address. to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. an- other erase suspend command can be written after the chip has resumed erasing.
AM29F016 15 write operation status table 6. write operation status notes: 1. performing successive read operations from the erase-suspended sector will cause dq2 to toggle. 2. performing successive read operations from any address will cause dq6 to toggle. 3. reading the byte address being programmed while in the erase-suspend program mode will indicate logic 1 at the dq2 bit. however, successive reads from the erase-suspended sector will cause dq2 to toggle. dq7 data polling the AM29F016 device features data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm, an attempt to read the device will produce the complement of the data last written to dq7. upon completion of the embedded program algorithm, an attempt to read the device will produce the true data last written to dq7. during the embedded erase algorithm, an attempt to read the device will produce a 0 at the dq7 output. upon completion of the embedded erase algorithm an at- tempt to read the device will produce a 1 at the dq7 output. the flowchart for data polling (dq7) is shown in figure 3. data polling will also flag the entry into erase suspend. dq7 will switch 0 to 1 at the start of the erase sus- pend mode. please note that the address of an erasing sector must be applied in order to observe dq7 in the erase suspend mode. during program in erase suspend, data polling will perform the same as in regular program execution out- side of the suspend mode. for chip erase, the data polling is valid after the rising edge of the sixth we pulse in the six write pulse sequence. for sector erase, the data polling is valid after the last rising edge of the sector erase we pulse. data polling must be performed at sector addresses within any of the sectors being erased and not a sector that is within a protected sector group. otherwise, the status may not be valid. just prior to the completion of embedded algorithm op- erations dq7 may change asynchronously while the output enable (oe ) is asserted low. this means that the device is driving status information on dq7 at one instant of time and then that bytes valid data at the next instant of time. depending on when the system sam- ples the dq7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operations and dq7 has a valid data, the data outputs on dq0Cdq6 may be still invalid. the valid data on dq0Cdq7 can be read on the successive read attempts. the data polling feature is only active during the em- bedded programming algorithm, embedded erase al- gorithm, erase suspend, erase-suspend-program mode, or sector erase time-out (see table 6). see figure 11 for the data polling timing specifications and diagrams. status dq7 dq6 dq5 dq3 dq2 in progress byte program in embedded program algorithm dq7 toggle 0 0 1 embedded program algorithm 0 toggle 0 1 toggle erase suspended mode erase suspended read (erase suspended sector) 1101 toggle (note 1) erase suspended read (non-erase suspended sector) data data data data data erase suspended read (non-erase suspended sector) dq7 toggle (note 2) 01 1 (note 3) exceeded time limits byte program in embedded program algorithm dq7 toggle 1 0 1 program/erase program in embedded program algorithm 0 toggle 1 1 n/a erase suspended mode erase suspended read (non-erase suspended sector) dq7 toggle 1 1 n/a
16 AM29F016 dq6 toggle bit i the AM29F016 also features the toggle bit i as a method to indicate to the host system that the embed- ded algorithms are in progress or completed. during an embedded program or erase algorithm cy- cle, successive attempts to read (oe toggling) data from the device at any address will result in dq6 tog- gling between one and zero. once the embedded pro- gram or erase algorithm cycle is completed, dq6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit i is valid after the rising edge of the fourth we pulse in the four write pulse sequence. for chip erase, the toggle bit i is valid after the rising edge of the sixth we pulse in the six write pulse sequence. for sector erase, the toggle bit i is valid after the last rising edge of the sector erase we pulse. the toggle bit i is active during the sector erase time out. either ce or oe toggling will cause the dq6 to toggle. in addition, an erase suspend/resume command will cause dq6 to toggle. see figure 12 for the toggle bit i timing specifications and diagrams. dq5 exceeded timing limits dq5 will indicate if the program or erase time has ex- ceeded the specified limits (internal pulse count). under these conditions dq5 will produce a 1. this is a failure condition which indicates that the program or erase cycle was not successfully completed. data poll- ing is the only operating function of the device under this condition. the ce circuit will partially power down the device under these conditions (to approximately 2 ma). the oe and we pins will control the output dis- able functions as described in table 1. the dq5 failure condition will also appear if a user tries to program a 1 to a location that is previously pro- grammed to 0. in this case the device locks out and never completes the embedded program algorithm. hence, the system never reads a valid data on dq7 bit and dq6 never stops toggling. once the device has ex- ceeded timing limits, the dq5 bit will indicate a 1. please note that this is not a device failure condition since the device was incorrectly used. if this occurs, reset the device. dq3 sector erase timer after the completion of the initial sector erase com- mand sequence the sector erase time-out will begin. dq3 will remain low until the time-out is complete. data polling and toggle bit i are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates the device has been written with a valid erase command, dq3 may be used to determine if the sector erase timer win- dow is still open. if dq3 is high (1) the internally con- trolled erase cycle has begun; attempts to write subsequent commands (other than erase suspend) to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit i. if dq3 is low (0), the device will accept additional sec- tor erase commands. to insure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 were high on the second sta- tus check, the command may not have been accepted. refer to table 6: write operation status. dq2 toggle bit ii this toggle bit, along with dq6, can be used to deter- mine whether the device is in the embedded erase al- gorithm or in erase suspend. successive reads from the erasing sector will cause dq2 to toggle during the embedded erase algorithm. if the device is in the erase-suspended-read mode, successive reads from the erase-suspend sector will cause dq2 to toggle. when the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sec- tor will indicate a logic 1 at the dq2 bit. dq6 is different from dq2 in that dq6 toggles only when the standard program or erase, or erase sus- pend program operation is in progress. the behavior of these two status bits, along with that of dq7, is summa- rized as follows: notes: 1. these status flags apply when outputs are read from a sector that has been erase-suspended. 2. these status flags apply when outputs are read from the byte address of the non-erase suspended sector. for example, dq2 and dq6 can be used together to determine the erase-suspend-read mode (dq2 toggles while dq6 does not). see also table 6 and figure 17. mode dq7 dq6 dq2 program dq7 toggles 1 erase 0 toggles toggles erase suspend read (1) (erase-suspended sector) 1 1 toggles erase suspend program dq7 (2) toggles 1 (2)
AM29F016 17 furthermore, dq2 can also be used to determine which sector is being erased. when the device is in the erase mode, dq2 toggles if this bit is read from the erasing sector. ry/by ready/busy the AM29F016 provides a ry/by open-drain output pin as a way to indicate to the host system that the em- bedded algorithms are either in progress or has been completed. if the output is low, the device is busy with either a program or erase operation. if the output is high, the device is ready to accept any read/write or erase operation. when the ry/by pin is low, the device will not accept any additional program or erase com- mands with the exception of the erase suspend com- mand. if the AM29F016 is placed in an erase suspend mode, the ry/by output will be high. during programming, the ry/by pin is driven low after the rising edge of the fourth we pulse. during an erase operation, the ry/by pin is driven low after the rising edge of the sixth we pulse. the ry/by pin will indicate a busy condition during the reset pulse. refer to figure 13 for a detailed timing diagram. the ry/by pin is pulled high in standby mode. since this is an open-drain output, several ry/by pins can be tied together in parallel with a pull-up resistor to v cc . reset hardware reset the AM29F016 device may be reset by driving the reset pin to v il . the reset pin must be kept low (v il ) for at least 500 ns. any operation in progress will be terminated and the internal state machine will be reset to the read mode 20 m s after the reset pin is driven low. if a hardware reset occurs during a pro- gram operation, the data at that particular location will be indeterminate. when the reset pin is low and the internal reset is complete, the device goes to standby mode and cannot be accessed. also, note that all the data output pins are tri-stated for the duration of the reset pulse. once the reset pin is taken high, the device requires 500 ns of wake up time until outputs are valid for read access. the reset pin may be tied to the system reset input. therefore, if a system reset occurs during the embed- ded program or erase algorithm, the device will be au- tomatically reset to read mode and this will enable the systems microprocessor to read the boot-up firmware from the flash memory. data protection the AM29F016 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transi- tions. during power up the device automatically resets the internal state machine in the read mode. also, with its control register architecture, alteration of the mem- ory contents only occurs after successful completion of specific multi-bus cycle command sequences. the device also incorporates several features to pre- vent inadvertent write cycles resulting from v cc power-up and power-down transitions or system noise. low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than 3.2 v (typically 3.7 v). if v cc < v lko , the com- mand register is disabled and all internal program/ erase circuits are disabled. under this condition the de- vice will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above 3.2 v. write pulse glitch protection noise pulses of less than 5 ns (typical) on oe , ce or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih or we = v ih . to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the device with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is auto- matically reset to the read mode on power-up.
18 AM29F016 embedded algorithms figure 1. embedded programming algorithm start programming completed last address ? write program command sequence (see below) data poll device increment address yes no 5555h/aah 2aaah/55h 5555h/a0h program address/program data 18805d-6 program command sequence (address/command):
AM29F016 19 embedded algorithms figure 2. embedded erase algorithm start erasure completed write erase command sequence (see below) data polling or toggle bit i successfully completed 5555h/aah 2aaah/55h 5555h/80h chip erase command sequence (address/command): 5555h/aah 2aaah/55h 5555h/10h 5555h/aah 2aaah/55h 5555h/80h individual sector/multiple sector erase command sequence (address/command): 5555h/aah sector address/30h sector address/30h sector address/30h 2aaah/55h additional sector erase commands are optional 18805c-7 to insure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 were high on the second status check, the command may not have been accepted.
20 AM29F016 figure 3. data polling algorithm dq7 is rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. start fail no yes dq7 = data ? no pass yes no yes dq7 = data ? dq5 = 1 ? yes read byte (dq0Cdq7) addr = va read byte (dq0Cdq7) addr = va va = byte address for programming = any of the sector addresses within the sector being erased during sector erase operation = valid address equals any non-protected sector group address during chip erase 18805d-8 18805d-10 figure 5. maximum negative overshoot waveform 20 ns 20 ns +0.8 v C0.5 v 20 ns C2.0 v
AM29F016 21 18805d-9 figure 4. toggle bit i algorithm start fail no yes dq6 = toggle ? pass yes no yes dq6 is rechecked even if dq5 = 1 because dq6 may stop toggling at the same time as dq5 changing to 1. dq6 = toggle ? dq5 = 1 ? yes read byte (dq0Cdq7) addr = dont care read byte (dq0Cdq7) addr = dont care no 18805d-11 figure 6. maximum positive overshoot waveform 20 ns v cc + 0.5 v 2.0 v 20 ns 20 ns v cc + 2.0 v
22 AM29F016 absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . C65 c to +125 c ambient temperature with power applied. . . . . . . . . . . . . . C55 c to +125 c voltage with respect to ground all pins except a9 (note 1). . . . . . . . .C2.0 v to +7.0 v v cc (note 1). . . . . . . . . . . . . . . . . . . .C2.0 v to +7.0 v a9, oe , reset (note 2) . . . . . . . . .C2.0 v to +13.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is C0.5 v. during voltage transitions, inputs may overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on output and i/o pins is v cc + 0.5 v. during voltage transitions, outputs may overshoot to v cc + 2.0 v for periods up to 20 ns. 2. minimum dc input voltage on a9, oe , reset pins is C0.5 v. during voltage transitions, a9, oe , reset pins may overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc input voltage on a9 is +12.5 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output shorted at a time. duration of the short circuit should not be greater than one second. stresses above those listed under absolute maximum rat- ings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure of the de- vice to absolute maximum rating conditions for extended peri- ods may affect device reliability. operating ranges commercial (c) devices case temperature (t c ). . . . . . . . . . . . . .0 c to +70 c industrial (i) devices case temperature (t c ). . . . . . . . . . . . C40 c to +85 c v cc supply voltages v cc for AM29F016-75 . . . . . . . . . +4.75 v to +5.25 v v cc for AM29F016-90, 120, 150. . +4.50 v to +5.50 v operating ranges define those limits between which the functionality of the device is guaranteed.
AM29F016 23 dc characteristics ttl/nmos compatible notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component (at 6 mhz). the frequency component typically is less than 1 ma/mhz, with oe at v ih . 2. i cc active while embedded program or erase algorithm is in progress. 3. not 100% tested. parameter symbol parameter description test description min max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 m a i lit a9 input load current v cc = v cc max, a9 = 12.0 volt 50 m a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 m a i cc1 v cc active current (note 1) ce = v il, oe = v ih 40 ma i cc2 v cc active current (notes 2, 3) ce = v il, oe = v ih 60 ma i cc3 v cc standby current v cc = v cc max, ce = v ih , reset = v ih 1.0 ma i cc4 v cc standby current (reset) v cc = v cc max, reset = v il 1.0 ma v il input low level C0.5 0.8 v v ih input high level 2.0 v cc + 0.5 v v id voltage for autoselect and sector protect v cc = 5.0 volt 11.5 12.5 v v ol output low voltage i ol = 12 ma, v cc = v cc min 0.45 v v oh output high level i oh = C2.5 ma v cc = v cc min 2.4 v v lko low v cc lock-out voltage 3.2 4.2 v
24 AM29F016 dc characteristics (continued) cmos compatible notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component (at 6 mhz). the frequency component typically is less than 1 ma/mhz, with oe at v ih . 2. i cc active while embedded program or erase algorithm is in progress. 3. not 100% tested. parameter symbol parameter description test description min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 m a i lit a9 input load current v cc = v cc max, a9 = 12.0 volt 50 m a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 m a i cc1 v cc active current (note 1) ce = v il, oe = v ih 25 40 ma i cc2 v cc active current (notes 2, 3) ce = v il, oe = v ih 30 40 ma i cc3 v cc standby current v cc = v cc max, ce = v cc 0.3 v, reset = v cc 0.3 v 15 m a i cc4 v cc standby current (reset) v cc = v cc max, reset = v ss 0.3 v 15 m a v il input low level C0.5 0.8 v v ih input high level 0.7 x v cc v cc + 0.3 v v id voltage for autoselect and sector protect v cc = 5.0 volt 11.5 12.5 v v ol output low voltage i ol = 12 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = C2.5 ma, v cc = v cc min 0.85 v cc v v oh2 i oh = C100 m a, v cc = v cc min v cc C 0.4 v v lko low v cc lock-out voltage 3.2 4.2 v
AM29F016 25 ac characteristics read-only operations characteristics notes: 1. test conditions (for -75): output load: 1 ttl gate and 30 pf input rise and fall times: 5 ns input pulse levels: 0.0 v to 3.0 v timing measurement reference level: 1.5 v input and output 2. test conditions (for all others): output load: 1 ttl gate and 100 pf input rise and fall times: 20 ns input pulse levels: 0.45 v to 2.4 v timing measurement reference level: 0.8 v and 2.0 v input and output 3. output driver disable time. 4. not 100% tested. parameter symbol parameter description test setup speed options (notes 1 and 2) unit jedec standard -75 -90 -120 -150 t avav t rc read cycle time 4 min 70 90 120 150 ns t avqv t acc address to output delay ce = v il oe = v il max 70 90 120 150 ns t elqv t ce chip enable to output delay oe = v il max 70 90 120 150 ns t glqv t oe output enable to output delay max 40 40 50 55 ns t ehqz t df chip enable to output high z (notes 3, 4) max20203035ns t ghqz t df output enable to output high z (notes 3, 4) max20203035ns t axqx t oh output hold time from addresses ce or oe whichever occurs first min0000ns t ready reset pin low to read mode 4 max20202020 m s 18805d-11 figure 7. test conditions 2.7 k w diodes = in3064 or equivalent c l 6.2 k w 5.0 volt in3064 or equivalent note: c l (for -75) = 30 pf including jig capacitance c l (for all others) = 100 pf including jig capacitance device under test
26 AM29F016 ac characteristics write/erase/program operations notes: 1. this does not include the preprogramming time. 2. not 100% tested. 3. these timings are for temporary sector group unprotect operation. parameter symbol parameter description speed options (notes 1 and 2) unit jedec standard -75 -90 -120 -150 t avav t wc write cycle time min 70 90 120 150 ns t avwl t as address setup time min0000ns t wlax t ah address hold time min40455050ns t dvwh t ds data setup time min 40 45 50 50 ns t whdx t dh data hold time min0000ns t oeh output enable hold time read 2 min0000ns toggle bit i and data polling 2 min10101010ns t ghwl t ghwl read recover time before write (oe high to we low) min0000ns t elwl t cs ce setup time min0000ns t wheh t ch ce hold time min0000ns t wlwh t wp write pulse width min 40 45 50 50 ns t whwl t wph write pulse width high min 20 20 20 20 ns t whwh1 t whwh1 byte programming operation typ7777 m s t whwh2 t whwh2 sector erase operation 1 typ1111sec max8888sec t vcs v cc set up time 2 min 50 50 50 50 m s t vidr rise time to v id (notes 2, 3) min 500 500 500 500 ns t vlht voltage transition time (notes 2, 3) min4444 m s t oesp oe setup time to we active (notes 2, 3)min4444 m s t rp reset pulse width min 500 500 500 500 ns t busy program/erase valid to ry/by delay min 40 40 50 60 ns
AM29F016 27 key to switching waveforms switching test waveform must be steady may change from h to l may change from l to h does not apply dont care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform inputs outputs ks000010-pal 18805d-12 figure 8. ac waveforms for read operations addresses ce oe we outputs addresses stable high z high z (t df ) (t ce ) (t oh ) output valid t acc t oe t rc t oeh
28 AM29F016 switching waveforms 18805d-13 figure 9. program operation timings d out pd t ah t rc data polling t df t oh t ce t oe t ds t cs t wph t dh t wp t ghwl addresses ce oe we data 5.0 volt notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. t wc t as dq 7 5555h pa a0h t whwh1 pa 3rd bus cycle t ah t as t wp t cs t dh 5555h 2aaah sa ce oe we data v cc aah 55h 80h aah 55h 10h/30h t wph addresses 2aaah t vcs t ds 5555h t ghwl 18805d-14 figure 10. ac waveforms chip/sector erase operations note: sa is the sector address for sector erase. addresses = dont care for chip erase. 5555h
AM29F016 29 switching waveforms 18805d-15 figure 11. ac waveforms for data polling during embedded algorithm operations dq0Cdq7 valid data t ch t oeh t oe t ce t whwh 1 or 2 dq7 = valid data high z ce oe we dq7 t oh t df dq 7 dq0Cdq6 dq0Cdq6 = invalid *dq7 = valid data (the device has completed the embedded opera- tion). * 18805d-16 figure 12. ac waveforms for toggle bit i during embedded algorithm operations ce t oeh we oe *dq6 stops toggling (the device has completed the embedded operation). dq6 = stop toggling dq0Cdq7 valid dq6 = toggle dq6 = toggle data (dq0Cdq7) * t oe
30 AM29F016 notes: 1. all protected sector groups unprotected. 2. all previously protected sector groups are protected once again. figure 15. temporary sector group unprotect algorithm 18805d-17 figure 13. ry/by timing diagram during program/erase operations ce we ry/by t busy entire programming or erase operations the rising edge of the last we signal 18805d-18 figure 14. reset timing diagram reset t ready t rp start perform erase or program operations reset = v ih temporary sector group unprotect completed (note 2) reset = v id (note 1) 18805d-21
AM29F016 31 figure 16. temporary sector group unprotect timing diagram ry/by program or erase command sequence 18805d-22 reset ce we 0v or 5 v 0 or 5v t vidr 12v 18805d-23 figure 17. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we dq6 dq2 toggle dq2 and dq6 with oe erase complete note: dq2 is read from the erase-suspended sector. erase suspend suspend program resume embedded erasing
32 AM29F016 ac characteristics write/erase/program operations alternate ce controlled writes notes: 1. this does not include the preprogramming time. 2. not 100% tested. parameter symbol parameter description speed options (notes 1 and 2) unit jedec standard -75 -90 -120 -150 t avav t wc write cycle time min 70 90 120 150 ns t avel t as address setup time min0000ns t elax t ah address hold time min40455050ns t dveh t ds data setup time min40455050ns t ehdx t dh address hold time min0000ns t oes output enable setup time (note 2) min0000ns t oeh output enable hold time read (note 2) min0000ns toggle bit i and data polling (note 2) min10101010ns t ghel t ghel read recover time before write min0000ns t wlel t ws ce setup time min0000ns t ehwh t wh ce hold time min0000ns t eleh t cp write pulse width min 40 45 50 50 ns t ehel t cph write pulse width high min 20 20 20 20 ns t whwh1 t whwh1 byte programming operation typ7777 m s t whwh2 t whwh2 sector erase operation (note 1) typ1111sec max8888sec
AM29F016 33 18805d-24 figure 18. alternate ce controlled program operation timing d out pd t ah data polling t ds t ws t cph t dh t cp t ghel addresses we oe ce data 5.0 volt notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. t wc t as dq 7 5555h pa a0h t whwh1 pa
34 AM29F016 erase and programming performance notes: 1. 25 c, 5 v v cc , 100,000 cycles. 2. although embedded algorithms allow for a longer chip program and erase time, the actual time will be considerably less since bytes program or erase significantly faster than the worst case byte. 3. under worst case condition of 90 c, 4.5 v v cc , 100,000 cycles. latchup characteristic includes all pins except v cc . test conditions: v cc = 5.0 volt, one pin at a time. tsop pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c, f = 1.0 mhz. parameter limits unit comments min typ max sector erase time 1 (note 1) 8 sec excludes 00h programming prior to erasure chip erase time 32 256 sec excludes 00h programming prior to erasure byte programming time 7 300 (note 3) m s excludes system-level overhead chip programming time 14.4 (note 1) 43.2 (notes 2, 3) sec excludes system-level overhead min max input voltage with respect to v ss on i/o pins C1.0 v v cc + 1.0 v v cc current C100 ma +100 ma parameter symbol parameter description test conditions min max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf
AM29F016 35 physical dimensions ts 048 48-pin standard thin small outline package 48 25 1 24 18.30 18.50 19.80 20.20 11.90 12.10 0.05 0.15 0.50 bsc 0.95 1.05 16-038-ts48-2 ts 048 da101 8-8-94 ae pin 1 i.d. 1.20 max 0.50 0.70 0.10 0.21 0.25mm (0.0098") bsc 0 5 0.08 0.20
36 AM29F016 physical dimensions tsr048 48-pin reversed thin small outline package trademarks copyright ? 1997 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies 48 25 1 24 18.30 18.50 19.80 20.20 11.90 12.10 seating plane 0.05 0.15 0.50 bsc 0.95 1.05 16-038-ts48 tsr048 da104 8-8-94 ae pin 1 i.d. 1.20 max 0.50 0.70 0.10 0.21 0.25mm (0.0098") bsc 0 5 0.08 0.20

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